Aluminum interconnection apparatus

ABSTRACT

A method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over the metal layer, patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process.

This application is a continuation-in-part of U.S. patent application Ser. No. 14/307,089, filed Jun. 17, 2014, and entitled “Aluminum Interconnection Apparatus,” which application is hereby incorporated herein by reference.

BACKGROUND

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for semiconductor devices having reliable aluminum based interconnection structures.

Aluminum based interconnection structures of a semiconductor device may comprise a plurality of lateral interconnections such as metal lines and a plurality of vertical interconnections such as vias. Various active circuits of the semiconductor may be coupled to external circuits through a variety of conductive channels formed by the vertical and lateral interconnections.

Aluminum based interconnection structures of a semiconductor device can be fabricated using suitable semiconductor fabrication techniques such as etching, Damascene and the like. In an etching based aluminum interconnection fabrication process, an aluminum layer is formed over a semiconductor substrate. According to the pattern of the aluminum interconnection structure, an etching process is applied to the aluminum layer to form a plurality of openings. A dielectric material is filled in the openings to isolate the remaining aluminum layer.

Alternatively, aluminum based interconnection structures may be formed by Damascene processes. Damascene processes can be divided into categories, namely single damascene processes and dual damascene processes. In single damascene technology, a metal via and its adjacent metal line may have different process steps. As a result, each may require a chemical mechanical planarization process to clean the surface. In contrast, in dual damascene technology, a metal via and its adjacent metal line may be formed within a single damascene trench. As a result, one CMP process is required in a dual damascene process to form the metal via and its adjacent metal line.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a cross sectional view of a semiconductor device having aluminum based interconnection structures in accordance with an embodiment;

FIG. 2 illustrates a cross sectional view of a semiconductor device after a first alloy layer is formed on a dielectric layer in accordance with an embodiment;

FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after an aluminum layer is formed on the first alloy layer in accordance with an embodiment;

FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after a second alloy layer is formed on the aluminum layer in accordance with an embodiment;

FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after an etching process is applied to the alloy layers and the aluminum layer in accordance with an embodiment;

FIG. 6 illustrates a cross sectional view of the semiconductor device shown in FIG. 5 after a dielectric material is filled in the openings shown in FIG. 5 in accordance with an embodiment;

FIG. 7 illustrates a cross sectional view of the semiconductor device shown in FIG. 6 after a second IMD layer is formed over the first IMD layer in accordance with an embodiment;

FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after a thermal process is applied to the semiconductor device in accordance with an embodiment;

FIG. 9 illustrates a semiconductor device prior to the formation of the interconnection structure in accordance with an embodiment;

FIG. 10 illustrates a cross sectional view of the semiconductor device shown in FIG. 9 after an opening is formed in the first IMD and the second IMD layer in accordance with an embodiment;

FIG. 11 illustrates a cross sectional view of the semiconductor device shown in FIG. 10 after an alloy layer is formed on the bottom and the sidewalls of the opening shown in FIG. 10 in accordance with an embodiment;

FIG. 12 illustrates a cross sectional view of the semiconductor device shown in FIG. 11 after a conductive material is deposited into the opening shown in FIG. 11 in accordance with an embodiment;

FIG. 13 illustrates a cross sectional view of the semiconductor device shown in FIG. 12 after a thermal process is applied to the semiconductor device in accordance with an embodiment;

FIG. 14 illustrates a cross sectional view of a semiconductor device after a first alloy layer is formed on a dielectric layer in accordance with various embodiments of the present disclosure;

FIG. 15 illustrates a cross sectional view of the semiconductor device shown in FIG. 14 after a metal layer is formed on the first alloy layer in accordance with various embodiments of the present disclosure;

FIG. 16 illustrates a cross sectional view of the semiconductor device shown in FIG. 15 after a second alloy layer is formed on the aluminum layer in accordance with various embodiments of the present disclosure;

FIG. 17 illustrates a cross sectional view of the semiconductor device shown in FIG. 16 after an etching process is applied to the first alloy layer, the aluminum layer and the second alloy layer in accordance with various embodiments of the present disclosure;

FIG. 18 illustrates a cross sectional view of the semiconductor device shown in FIG. 17 after a dielectric material is deposited over the metal structure in accordance with various embodiments of the present disclosure;

FIG. 19 illustrates a cross sectional view of the semiconductor device shown in FIG. 18 after a planarization process is performed to remove excess conductive materials in accordance with various embodiments of the present disclosure;

FIG. 20 illustrates a cross sectional view of the semiconductor device shown in FIG. 19 after a second IMD layer is formed over the first IMD layer in accordance with various embodiments of the present disclosure; and

FIG. 21 illustrates a flow chart of a method for forming the semiconductor device shown in FIG. 20 in accordance with various embodiments of the present disclosure.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The present disclosure will be described with respect to embodiments in a specific context, an aluminum alloy based interconnection apparatus. The disclosure may also be applied, however, to a variety of semiconductor devices. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

FIG. 1 illustrates a cross sectional view of a semiconductor device having aluminum based interconnection structures in accordance with an embodiment. As shown in FIG. 1, the semiconductor device 100 comprises a substrate 102. The substrate 102 may be a silicon substrate. Alternatively, the substrate 102 may be a silicon-on-insulator substrate. The substrate 102 may further comprise a variety of electrical circuits (not shown). The electrical circuits formed on the substrate 102 may be any type of circuitry suitable for a particular application.

In accordance with an embodiment, the electrical circuits may include various n-type metal-oxide semiconductor (NMOS) and/or p-type metal-oxide semiconductor (PMOS) devices such as transistors, capacitors, resistors, diodes, photo-diodes, fuses and the like. The electrical circuits may be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry or the like. One of ordinary skill in the art will appreciate that the above examples are provided for illustrative purposes only to further explain applications of the present disclosure and are not meant to limit the present disclosure in any manner.

An interlayer dielectric layer 104 is formed on top of the substrate 102. The interlayer dielectric layer 104 may be formed, for example, of a low-K dielectric material, such as silicon oxide. The interlayer dielectric layer 104 may be formed by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD) and plasma enhanced chemical vapor deposition (PECVD). It should also be noted that one skilled in the art will recognize that the interlayer dielectric layer 104 may further comprise a plurality of dielectric layers.

A bottom metal line layer 106 is formed over the interlayer dielectric layer 104. As shown in FIG. 1, the bottom metal line layer 106 may comprise a metal line 108. The metal line 108 is formed of a metal material such as an aluminum copper alloy. In addition, there may be two barrier layers (not shown) formed underneath and on top of the metal line 108 respectively. The bottom metal line layer 106 and the metal line 108 may be formed through any suitable fabrication techniques (e.g., deposition, single damascene and the like). The detailed structure and fabrication steps of the metal line 108 will be described below with respect to FIGS. 2-8.

A top via layer 114 is formed over the bottom metallization layer 106. A top metal line layer 120 is formed over the top via layer 114. As shown in FIG. 1, there may be two metal lines 122 and 124 embedded in the top metal line layer 120. The metal line 122 is coupled to a via 116. The via 116, the metal line 122 and the metal line 124 are formed of metal materials such as an aluminum copper alloy. The metal line 122 and the via 116 form a T-shaped damascene structure. Such a T-shaped damascene structure may be formed by using the dual damascene technique. The detailed structure and formation process of the T-shaped damascene structure will be described below with respect to FIGS. 9-13.

It should be noted while FIG. 1 shows the bottom metal line layer 106 and the top metal line layer 120, one skilled in the art will recognize that one or more inter-metal dielectric layers (not shown) and the associated metallization layers (not shown) are formed between the bottom metal line layer 106 and the top metal line layer 120. In particular, the layers formed over the bottom metal line layer 106 and under the top metal line layer 120 may be formed by alternating layers of lateral interconnection structures (e.g., metal lines) and vertical interconnection structures (e.g., vias).

FIGS. 2-8 illustrate intermediate stages of an etching process of forming the aluminum interconnection structures (e.g., metal line 108) shown in FIG. 1 in accordance with an embodiment. There may be a plurality of interconnection structures in the semiconductor device of FIG. 1. The fabrication techniques of the interconnection structures are similar, and hence only one interconnection structure is selected to illustrate the innovative aspects of various embodiments.

FIG. 2 illustrates a cross sectional view of a semiconductor device after a first alloy layer is formed on a dielectric layer in accordance with an embodiment. As shown in FIG. 2, the first alloy layer 204 is formed on top of the dielectric layer 202. The first alloy layer 204 is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and the like. The first alloy layer 204 may be formed by using suitable fabrication techniques such as CVD, physical vapor deposition (PVD) and the like.

FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after an aluminum layer is formed on the first alloy layer in accordance with an embodiment. The aluminum layer 302 may be formed of suitable fabrication techniques such as sputtering, PVD, CVD, electrochemical plating and the like. The thickness of the aluminum layer 302 is in a range from about 3000 angstroms to about 10000 angstroms. It should be noted that the thickness of the aluminum layer 302 is determined based upon the current carrying ability of the interconnection structures. The thickness range described above is selected purely for demonstration purposes and is not intended to limit the various embodiments of the present invention to any particular thickness.

FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after a second alloy layer is formed on the aluminum layer in accordance with an embodiment. As shown in FIG. 4, the second alloy layer 402 is formed on top of the aluminum layer 302. The second alloy layer 402 is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and the like. The second alloy layer 402 may be formed by using suitable fabrication techniques such as CVD, PVD and the like.

FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after an etching process is applied to the alloy layers and the aluminum layer in accordance with an embodiment. The alloy layers (e.g., 204 and 402) and the aluminum layer 302 are etched according to the pattern of the interconnect structure (e.g., metal line 108) of the semiconductor device. A plurality of openings such as 502 and 504 are formed by using suitable etching processes including dry etching such as reactive ion etching (RIE). The remaining portion of the alloy layers and the aluminum layer form an interconnection structure 506. As shown in FIG. 5, the interconnection structure 506 includes two alloy layers and an aluminum layer sandwiched between two alloy layers.

FIG. 6 illustrates a cross sectional view of the semiconductor device shown in FIG. 5 after a dielectric material is filled in the openings shown in FIG. 5 in accordance with an embodiment. A dielectric material is filled in the openings 502 and 504 (shown in FIG. 5) to form a first inter-metal dielectric (IMD) layer 602. The first IMD layer 602 may be formed of a low-K dielectric material, such as silicon oxide, fluorosilicate glass (FSG), Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof and the like. The first IMD layer 602 may be formed by suitable fabrication process such as CVD, PECVD, high-density plasma chemical vapor deposition (HDPCVD) or the like.

FIG. 7 illustrates a cross sectional view of the semiconductor device shown in FIG. 6 after a second IMD layer is formed over the first IMD layer in accordance with an embodiment. The formation of the second IMD layer 702 is similar to that of the first IMD layer 602, and hence is not discussed herein to avoid repetition.

FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after a thermal process is applied to the semiconductor device in accordance with an embodiment. The semiconductor device shown in FIG. 7 is placed in a high temperature environment to help copper dissolve into the aluminum layer 302. In accordance with an embodiment, the temperature of the thermal process is in a range from 300 degrees to 660 degrees. Copper particles 802 dissolve into the aluminum layer and form a copper aluminum alloy layer. The percentage of copper in such an aluminum copper alloy layer is in a range from about 0.5% to about 5.5%.

One advantageous feature of having an aluminum copper alloy layer is that the aluminum atoms may be of a plurality of high quality {111} crystal planes because the aluminum atoms may inherit some of the characteristics of other elements (e.g., copper) of the alloy. In particular, the aluminum atoms of the aluminum copper alloy may be of the same packed planes (e.g., the {111} close packed planes) as the copper of the alloy. Such {111} crystal planes help to enhance the structural integrity. As a result, the electro-migration issue may be improved. Another advantageous feature of having an aluminum copper alloy layer is that the aluminum layer and the copper alloy layer may form metal-to-metal boding rather than conventional metal-to-ceramic boding (e.g., Al-to-TiN). The metal-to-metal bonding helps to reduce the stress induced mismatch in the semiconductor device.

FIG. 8 further illustrates two metal oxide or metal silicide layers after the thermal process is applied to the semiconductor device. As described above with respect to FIGS. 2 and 4, the first alloy layer and the second alloy layer may be formed of copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys. After the copper portion of the alloy dissolves into the aluminum layer, the remaining metals (e.g., manganese) may diffuse into the dielectric layers (e.g., 202 and 702) adjacent to the first alloy layer and the second alloy layer respectively. Such a diffusion process leads to two barrier layers 802 and 804 respectively. The barrier layers 802 and 804 are formed of metal oxide or metal silicide.

One advantageous feature having the barrier layers formed of metal oxide or metal silicide is that this self-forming barrier of metal oxide or silicide may help to prevent copper from diffusing into the surrounding dielectric film.

FIGS. 9-13 illustrate intermediate stages of a dual damascene process of forming the aluminum interconnection structures shown in FIG. 1 in accordance with an embodiment. FIG. 9 illustrates a semiconductor device prior to the formation of the interconnection structure in accordance with an embodiment. The dielectric layer 902 is similar to the dielectric layer 202 shown in FIG. 2, and hence is not discussed herein. The first IMD layer 904 and the second IMD layer 906 are formed over the dielectric layer 902. The formation of the IMD layers 904 and 906 is similar to the IMD layer 702 shown in FIG. 7, and hence is not discussed again. It should be noted that according to the dual damascene process, the first IMD layer 904 and the second IMD layer 906 are alternatively referred to as a via IMD layer 904 and a trench IMD layer 906 respectively.

FIG. 10 illustrates a cross sectional view of the semiconductor device shown in FIG. 9 after an opening is formed in the first IMD and the second IMD layer in accordance with an embodiment. The opening 1002 may be formed by etching the first IMD layer 904 and the second IMD layer 906 respectively. The first IMD layer 904 and the second IMD layer 906 may be of different etching characteristics. As a result, the first IMD layer 904 may function as an etch stop layer when the second IMD layer 906 is etched. After the trench is formed, another etching process is applied to the first IMD layer 904 to form the via.

According to another embodiment, the opening may be formed by using two photolithographic patterning and anisotropic etching steps. In particular, a via opening is first formed through a first photolithographic patterning process and a first etching process. After the via is formed, similar patterning and etching processes are applied to the semiconductor device again to form an overlying trench opening. As shown in FIG. 10, the via opening and the trench opening form a T-shaped damascene structure.

FIG. 11 illustrates a cross sectional view of the semiconductor device shown in FIG. 10 after an alloy layer is formed on the bottom and the sidewalls of the opening shown in FIG. 10 in accordance with an embodiment. As shown in FIG. 11, the alloy layer 1102 is formed on the interior surface of the opening 1002. The alloy layer 1102 is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and the like. Alternatively, the second alloy layer 1102 may be replaced by a reactive manganese film. The second alloy layer 1102 may be formed by using suitable semiconductor fabrication techniques such as CVD, PVD and the like.

FIG. 12 illustrates a cross sectional view of the semiconductor device shown in FIG. 11 after a conductive material is deposited into the opening shown in FIG. 11 in accordance with an embodiment. The conductive material may be aluminum. The conductive material may be deposited into the opening using suitable techniques such as sputtering and the like. It should be noted that the sputtering process may not fully fill the opening. There may be an overhang 1202, which leads to a void or a plurality of voids embedded in the aluminum material filled in the opening.

FIG. 13 illustrates a cross sectional view of the semiconductor device shown in FIG. 12 after a thermal process is applied to the semiconductor device in accordance with an embodiment. The semiconductor device shown in FIG. 12 is placed in a high temperature environment, which helps to melt the metal material (e.g., aluminum). The melted material fills the void show in FIG. 12. In addition, the high temperature helps copper dissolve into the aluminum layer. According to an embodiment, the temperature of the thermal process is in a range from 300 degrees to 548 degrees. Copper particles 1302 dissolve into the aluminum layer and form a copper aluminum alloy, even some compound formation (e.g., CuAl₂). Alternatively, if the alloy layer is a manganese film, the manganese film may react with the aluminum layer to form MnAl₆. After the thermal process, a chemical mechanical polish (CMP) process is employed to remove overlying copper and polish the surface.

One advantageous feature of having an aluminum copper alloy layer is that the aluminum may form a plurality of high quality {111} crystal planes because the aluminum atoms may inherit some of the characteristics of other elements of the alloy. In particular, the aluminum atoms of the alloy may be of the same packed planes (e.g., the {111} close packed planes) as the copper of the alloy. Such {111} crystal planes help to enhance the structural integrity. As a result, the electro-migration issue may be reduced. In addition, the thermal process described above helps to improve the uniformity of the top surface of the semiconductor device shown in FIG. 13. As a result, the uniformity improvement is due to aluminum overburden reduction that can shorten the CMP process time so as to improve resistance (Rs) uniformity.

FIG. 13 further illustrates a metal oxide or metal silicide layer after the thermal process is applied to the semiconductor device. As described above with respect to FIG. 11, the alloy layer 1102 may be formed of copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys. After the copper portion of the alloy dissolves into the aluminum layer, the remaining metals (e.g., manganese) may diffuse into the dielectric layers (e.g., 902, 904 and 906) adjacent to the alloy layer 1102. Such a diffusion process leads to a barrier layer 1304 formed of metal oxide or metal silicide.

One advantageous feature is that the aluminum layer and the copper layers form metal-to-metal bonding rather than conventional metal-to-ceramic bonding. The metal-to-metal bonding helps to reduce the stress induced mismatch between two adjacent layers. In addition, the copper portion of the alloy may react with the aluminum layer to generate a good gap-fill material. Such a gap-fill material helps to reliably fill the void shown in FIG. 12.

FIGS. 14 to 20 illustrate intermediate steps of fabricating a semiconductor device having an aluminum alloy based interconnection apparatus in accordance with various embodiments of the present disclosure. FIG. 14 illustrates a cross sectional view of a semiconductor device after a first alloy layer is formed on a dielectric layer in accordance with various embodiments of the present disclosure. As shown in FIG. 14, the first alloy layer 1404 is formed on top of the dielectric layer 1402. The dielectric layer 1402 is similar to the interlayer dielectric layer 104 shown in FIG. 1, and hence is not discussed again to avoid unnecessary repetition.

In some embodiments, the first alloy layer 1404 is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and the like. The first alloy layer 1404 may be formed by using suitable semiconductor fabrication techniques such as CVD, PVD and/or the like.

FIG. 15 illustrates a cross sectional view of the semiconductor device shown in FIG. 14 after a metal layer is formed on the first alloy layer in accordance with various embodiments of the present disclosure. In some embodiments, the metal layer 1502 comprises aluminum. Throughout the description, the metal layer 1502 may be alternatively referred to as the aluminum layer 1502.

The aluminum layer 1502 may be formed of suitable fabrication techniques such as sputtering, PVD, CVD, electrochemical plating and/or the like. In some embodiments, the thickness of the aluminum layer 1502 is in a range from about 3000 angstroms to about 10000 angstroms.

It should be noted that the thickness of the aluminum layer 1502 is determined based upon different applications and design needs such as the current carrying ability of the interconnection structures. The thickness range described above is selected purely for demonstration purposes and is not intended to limit the various embodiments of the present disclosure to any particular thickness.

FIG. 16 illustrates a cross sectional view of the semiconductor device shown in FIG. 15 after a second alloy layer is formed on the aluminum layer in accordance with various embodiments of the present disclosure. As shown in FIG. 16, the second alloy layer 1602 is formed on top of the aluminum layer 1502. In accordance with some embodiments, the thickness of the second alloy layer 1602 may be approximately equal to the thickness of the first alloy layer 1404.

The second alloy layer 1602 is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and/or the like. The second alloy layer 1602 may be formed by using suitable fabrication techniques such as CVD, PVD and/or the like.

FIG. 17 illustrates a cross sectional view of the semiconductor device shown in FIG. 16 after an etching process is applied to the first alloy layer, the aluminum layer and the second alloy layer in accordance with various embodiments of the present disclosure. The first alloy layer 1404, the aluminum layer 1502 and the second alloy layer 1602 are etched according to the pattern of the interconnect structure (e.g., metal line 108) of the semiconductor device 100 shown in FIG. 1.

A plurality of openings 1702 and 1704 are formed by using suitable etching processes including dry etching such as reactive ion etching (RIE). The remaining portion of the alloy layers and the aluminum layer form a metal structure 1706. As shown in FIG. 17, the metal structure 1706 includes two alloy layers and an aluminum layer sandwiched between two alloy layers. The metal structure 1706 is over the dielectric layer 1402. In some embodiments, the metal structure 1706 is a metal line of the semiconductor device 100 shown in FIG. 1 above.

FIG. 18 illustrates a cross sectional view of the semiconductor device shown in FIG. 17 after a dielectric material is deposited over the metal structure in accordance with various embodiments of the present disclosure. A first inter-metal dielectric (IMD) layer 1802 may be formed of a low-K dielectric material, such as silicon oxide, fluorosilicate glass (FSG), Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof and the like. The first IMD layer 1802 is formed over the dielectric layer 1402 through a high temperature deposition process such as a CVD process.

It should be noted that the CVD process used in the previous example is selected purely for demonstration purposes and are not intended to limit the various embodiments of the present disclosure to any particular deposition processes. The first IMD layer 1802 may be formed by other suitable fabrication process such as PECVD, HDPCVD and/or the like.

The CVD process is of a temperature in a range from about 300 degrees to about 400 degrees. In alternative embodiments, the temperature of the CVD process is in a range from about 300 degrees to about 660 degrees. The semiconductor device is placed in such a high temperature environment for about 1 to 2 minutes. The high temperature environment of the CVD process helps copper of the alloy layers 1404 and 1602 dissolve into the aluminum layer 1502. In accordance with an embodiment, the temperature of the CVD process is in a range from 300 degrees to 660 degrees. Copper particles 1808 dissolve into the aluminum layer 1502 and form a copper aluminum alloy layer. The percentage of copper in such an aluminum copper alloy layer is in a range from about 0.5% to about 5.5%.

One advantageous feature of having an aluminum copper alloy layer is that the aluminum atoms may be of a plurality of high quality {111} crystal planes because the aluminum atoms may inherit some of the characteristics of other elements (e.g., copper) of the alloy. In particular, the aluminum atoms of the aluminum copper alloy may be of the same packed planes (e.g., the {111} close packed planes) as the copper of the alloy. Such {1111} crystal planes help to enhance the structural integrity. As a result, the electro-migration issue may be improved.

Another advantageous feature of having an aluminum copper alloy layer is that the aluminum layer and the copper alloy layer may form metal-to-metal boding rather than conventional metal-to-ceramic boding (e.g., Al-to-TiN). The metal-to-metal bonding helps to reduce the stress induced mismatch in the semiconductor device 100 shown in FIG. 1.

FIG. 18 further illustrates two metal oxide or metal silicide layers after the high temperature deposition process is applied to the semiconductor device. As described above with respect to FIGS. 14 and 16, the first alloy layer and the second alloy layer may be formed of copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys. After the copper portion of the alloy dissolves into the aluminum layer, the remaining metals (e.g., manganese) may diffuse into the portions of the dielectric layers (e.g., 1402 and 1802) adjacent to the first alloy layer 1404 and the second alloy layer 1602 respectively. Such a diffusion process leads to two barrier layers 1804 and 1806 respectively. In some embodiments, the barrier layers 1804 and 1806 are formed of metal oxide. In alternative embodiments, the barrier layers 1804 and 1806 are formed of metal silicide.

One advantageous feature having the barrier layers formed of metal oxide or metal silicide is that this self-forming barrier of metal oxide or silicide may help to prevent copper from diffusing into the surrounding dielectric film.

FIG. 19 illustrates a cross sectional view of the semiconductor device shown in FIG. 18 after a planarization process is performed to remove excess conductive materials in accordance with various embodiments of the present disclosure. The planarization process may be implemented by using suitable techniques such as grinding, polishing and/or chemical etching, a combination of etching and grinding techniques.

In accordance with various embodiments, the planarization process may be implemented by using a CMP process. In the CMP process, a combination of etching materials and abrading materials are put into contact with the top surface of the semiconductor device and a grinding pad (not shown) is used to grind away excess conductive materials until the top surface of the first IMD layer 1802 is substantially level with the top surfaces of the second barrier layer 1806.

FIG. 20 illustrates a cross sectional view of the semiconductor device shown in FIG. 19 after a second IMD layer is formed over the first IMD layer in accordance with various embodiments of the present disclosure. The formation of the second IMD layer 2002 is similar to that of the first IMD layer 1802, and hence is not discussed herein to avoid repetition.

FIG. 21 illustrates a flow chart of a method for forming the semiconductor device shown in FIG. 20 in accordance with various embodiments of the present disclosure. This flowchart is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various step as illustrated in FIG. 21 may added, removed, replaced, rearranged and repeated.

At step 2102, a first alloy layer is deposited over a dielectric layer. The first alloy layer is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and/or the like.

At step 2104, an aluminum layer is formed over the first alloy layer through suitable fabrication techniques such as sputtering, PVD, CVD, electrochemical plating and the like. The thickness of the aluminum layer is in a range from about 3000 angstroms to about 10000 angstroms.

At step 2106, a second alloy layer is deposited over the aluminum layer. The second alloy layer is formed of copper alloys including copper manganese alloys, copper chromium alloys, copper vanadium alloys, copper niobium alloys, copper titanium alloys, any combinations thereof and/or the like.

At step 2108, a suitable etching process is applied to the first alloy layer, the aluminum layer and the second alloy layer to form a metal structure. The etching process may be a RIE process.

At step 2112, a dielectric layer is deposited over the metal structure through a CVD process. The metal structure is embedded in the dielectric layer. The CVD process is of a temperature in a range from about 300 degrees to about 660 degrees. The high temperature of the CVD process helps copper of the first alloy layer and the second alloy layer dissolve into the aluminum layer to form a copper aluminum alloy layer.

In addition, the high temperature of the CVD process help the metals (e.g., manganese) of the first alloy layer and the second alloy layer diffuse into the adjacent dielectric layers to form two barrier layers. The barrier layers may be formed of metal oxide. Alternatively, the barrier layers may be formed of metal silicide.

At step 2114, a CMP process is applied to the excess material until the top surface of the dielectric layer is substantially level with the top surface of the metal structure.

At step 2116, a dielectric material is deposited over the top surfaces of the metal structure as well as the dielectric layer.

In accordance with an embodiment, a method comprises forming a metal structure over a substrate, wherein the metal structure comprises a first alloy layer over a first dielectric layer and a metal layer over the first alloy layer, depositing a second dielectric layer over the substrate through a deposition process, wherein the metal structure is embedded in the second dielectric layer and forming a first barrier through a first reaction between the first alloy layer and the first dielectric layer and a metal alloy through a second reaction between the first alloy layer and the metal layer.

In accordance with an embodiment, a method comprises depositing a first alloy layer over a first dielectric layer, wherein the first alloy layer is formed of copper and a first metal, and wherein the first metal is selected from the group consisting of manganese, chromium, vanadium, niobium and titanium, depositing an aluminum layer over the first alloy layer, patterning the first alloy layer and the aluminum layer to form a metal structure, and depositing a second dielectric layer over the first dielectric layer through a deposition process, wherein the metal structure is embedded in the second dielectric layer, a first barrier layer is generated through a first reaction between the first metal of the first alloy layer and a dielectric material of the first dielectric layer and a copper aluminum alloy is generated through a second reaction between the copper of the first alloy layer and the aluminum layer.

In accordance with an embodiment, a method comprises depositing a first alloy layer over a substrate, depositing a metal layer over the first alloy layer, depositing a second alloy layer over the metal layer, patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A method comprising: forming a metal structure over a substrate, wherein the metal structure comprises: a first alloy layer over a first dielectric layer; and a metal layer over the first alloy layer; depositing a second dielectric layer over the substrate through a deposition process, wherein the metal structure is embedded in the second dielectric layer; and forming a first barrier through a first reaction between the first alloy layer and the first dielectric layer and a metal alloy through a second reaction between the first alloy layer and the metal layer.
 2. The method of claim 1, wherein the first alloy layer comprises copper alloys; the metal layer comprises aluminum; and the metal alloy is a copper aluminum alloy.
 3. The method of claim 1, further comprising: depositing a second alloy layer over the metal layer.
 4. The method of claim 3, further comprising: forming a second barrier layer over the second alloy layer, wherein the second barrier layer is generated by a third reaction between the second alloy layer and an adjacent dielectric layer during the deposition process.
 5. The method of claim 1, wherein: the deposition process is a chemical vapor deposition (CVD) process.
 6. The method of claim 5, wherein: the CVD process is of a temperature in a range from about 300 degrees to about 660 degrees.
 7. The method of claim 1, wherein: the first alloy layer comprises a first metal and a second metal, and wherein the first metal is copper and the second metal is selected from the group consisting of manganese, chromium, vanadium, niobium and titanium.
 8. A method comprising: depositing a first alloy layer over a first dielectric layer, wherein the first alloy layer is formed of copper and a first metal, and wherein the first metal is selected from the group consisting of manganese, chromium, vanadium, niobium and titanium; depositing an aluminum layer over the first alloy layer; patterning the first alloy layer and the aluminum layer to form a metal structure; and depositing a second dielectric layer over the first dielectric layer through a deposition process, wherein: the metal structure is embedded in the second dielectric layer; a first barrier layer is generated through a first reaction between the first metal of the first alloy layer and a dielectric material of the first dielectric layer; and a copper aluminum alloy is generated through a second reaction between the copper of the first alloy layer and the aluminum layer.
 9. The method of claim 8, further comprising: depositing a second alloy layer over the aluminum layer; and patterning the first alloy layer, the aluminum layer and the second alloy layer to form the metal structure.
 10. The method of claim 9, further comprising: forming a second barrier layer over the second alloy layer.
 11. The method of claim 10, further comprising: applying the deposition process to the aluminum layer, the first alloy layer and the second alloy layer to form: the second barrier layer through a third reaction between the second alloy layer and a dielectric material of an adjacent dielectric layer.
 12. The method of claim 8, further comprising: applying a chemical mechanical polish (CMP) process to the second dielectric layer; and depositing a third dielectric layer over the second dielectric layer.
 13. The method of claim 12, wherein: the deposition process is a chemical vapor deposition (CVD) process.
 14. The method of claim 13, wherein: the CVD process is of a temperature from 300 degrees to 660 degrees.
 15. A method comprising: depositing a first alloy layer over a substrate; depositing a metal layer over the first alloy layer; depositing a second alloy layer over the metal layer, wherein a bottom surface of the second alloy layer is in direct contact with a top surface of the metal layer; patterning the first alloy layer, the metal layer and the second alloy layer to form a metal structure; and depositing a dielectric layer over the metal structure through a chemical vapor deposition (CVD) process.
 16. The method of claim 15, further comprising: forming a first barrier layer and a second barrier layer through the CVD process, wherein the CVD process is of a temperature greater than 300 degrees, and wherein: the first barrier layer is underneath the first alloy layer; and the second barrier layer is over the second alloy layer.
 17. The method of claim 16, wherein: the first barrier layer is formed by a first reaction between the first alloy layer and adjacent dielectric materials; and the second barrier layer is formed by a second reaction between the second alloy layer and adjacent dielectric materials.
 18. The method of claim 15, further comprising: depositing the dielectric layer over the metal structure, wherein the metal structure is embedded in the dielectric layer.
 19. The method of claim 18, further comprising: applying a chemical mechanical polish process to removing excess materials above the metal structure.
 20. The method of claim 15, further comprising: the first alloy layer and the second alloy layer comprise copper alloys. 